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Prof. Dr. John Patrick Hayes

Profile

Academic positionFull Professor
Research fieldsComputer Architecture, Embedded and Massively Parallel Systems,Production Systems, Operations Management, Quality Management and Factory Planning,Automation, Mechatronics, Control Systems, Intelligent Technical Systems, Robotics
KeywordsDefektmodellierung, Fehlersimulation, Quanten-Schaltkreise, Systems-on-a-chip, Testgenerierung

Current contact address

CountryUnited States of America
CityAnn Arbor
InstitutionUniversity of Michigan
InstituteDepartment of Electrical Engineering and Computer Science
Homepagehttp://web.eecs.umich.edu/~jhayes/

Host during sponsorship

Prof. Dr. Bernd BeckerInstitut für Informatik, Albert-Ludwigs-Universität Freiburg, Freiburg
Prof. Dr. Ilia PolianFakultät für Informatik und Mathematik, Universität Passau, Passau
Prof. Dr. Ilia PolianInstitut für Technische Informatik (ITI), Universität Stuttgart, Stuttgart
Start of initial sponsorship01/02/2004

Programme(s)

2003Humboldt Research Award Programme

Nominator's project description

Professor Hayes is one of the most prominent researchers worldwide in the area of computer architecture and design actively involved in the development of the area since more than 30 years. His research in logic design and testing, very large-scale integrated (VLSI) circuit design, and fault-tolerant computer architectures has been significantly contributing to the state-of-the-art in the field. As an example we mention his early work on fault and circuit modelling for test generation purposes which influenced commercial logic simulators and a generation of academic researchers as well. More recently he is actively in design and testability issues of quantum circuits demonstrating his openness and interest also in the latest developments. At the Faculty of Applied Sciences in Freiburg he plans to perform research on Test and Verification of Nanoscale Digital Circuits in collaboration with the group of Professor Bernd Becker.

Publications (partial selection)

2017Florian Neugebauer, Ilia Polian, John P. Hayes: Building a better random number generator for stochastic computing. In: Proceedings of Euromicro Conference on Digital System Design, 2017, 1-6
2017Florian Neugebauer, Ilia Polian, John P. Hayes: Framework for quantifying and managing accuracy in stochastic circuit design. In: Proceedings of 20th Design Automation and Test in Europe Conference, 2017, 1-6
2013Alexandru Paler, Josef Kinseher, Ilia Polian, John P. Hayes: Approximate simulation of circuits with probabilistic behavior. In: Proceedings of 26th Symposium on Defect & Fault Tolerance in VLSI and Nano. Systems, 2013, 95-100
2012Alexandru Paler, Ilia Polian, John P. Hayes: Detection and diagnosis of faulty quantum circuits. In: Proceedings of 17th Asia and South Pacific Design Automation Conference, 2012, 181-186
2011Ilia Polian, John Patrick Hayes, Sudhakar M. Reddy, Bernd Becker: Modeling and mitigating transient errors in logic circuits. In: IEEE Transactions on Dependable and Secure Computing, 2011, 537-547
2011Ilia Polian, John Patrick Hayes: Selective hardening: toward cost-effective fault tolerance. In: IEEE Design and Test of Computers, 2011, 54-63
2011Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes: Tomographic testing and validation of probabilistic circuits. In: Proceedings of 16th European Test Symposium, 2011, 63-68
2007John P. Hayes, Ilia Polian, Bernd Becker: An analysis framework for transient-error tolerance. In: Proceedings of 25th VLSI Test Symposium, 2007, 249-255
2007Ilia Polian, John P. Hayes, Damian Nowroth, Bernd Becker: Ein kostentbegrentzer Ansatz zur Reduktion der transienten Fehlerrate. In: GMM Fachbericht 52: Zuverlässigkeit und Entwurf, 2007, 183-184
2005Ilia Polian, John P. Hayes, Thomas Fiehn, Bernd Becker: A family of logical fault models for reversible circuits. In: Proceedings of 14th Asian Test Symposium, 2005, 422-428
2005Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker: Transient fault characterization in dynamic noisy environments. In: Proceedings of the 36th International Test Conference, 2005, 1039-1048
2004John P. Hayes, Ilia Polian, Bernd Becker: Testing for missing-gate faults in reversible circuits. In: Proceedings of 13th Asian Test Symposium, 2004, 100-105